High-speed networks are continually evolving. The evolution includes a continuing advancement in the operational speed of the networks. The network implementation of choice that has emerged is Ethernet networks physically connected over twisted pair wiring. One of the most prevalent high speed LANs (local area network) for providing connectivity between personal computers, workstations and servers is Ethernet in its 10BASE-T form.
High-speed LAN technologies include 100BASE-T (Fast Ethernet) and 1000BASE-T (Gigabit Ethernet). Fast Ethernet technology has provided a smooth evolution from the 10 megabits per second (Mbps) performance of 10BASE-T to the 100 Mbps performance of 100BASE-T. Gigabit Ethernet provides 1 Gigabit per second (Gbps) data rate with essentially the simplicity of Ethernet. There is a desire to push operating performance to even greater data rates.
Increases in the speeds of communication networks require increases in the speeds of ADCs used in the communication networks. A time-interleaved ADC architecture can effectively provide high-speed analog to digital conversion with ADCs that individually operate at much lower frequencies than the analog to digital conversion. Therefore, a time-interleaved ADC architecture can be used to increase the effective operational frequency of the ADCs.
FIG. 1 shows a time interleaved analog to digital converter architecture. A plurality of N sub-sample, sample and hold circuits 110, 112, 114 receive an analog signal. Clocks to each of the sample and hold circuits operate at a frequency of Fs/N, and include a phase of approximately (360/N)*(i−1), in which i varies from 1 to N. Each of the sample and hold circuits sample the incoming analog signal at calculated moments in time. The samples are input to corresponding M-bit ADCs 120, 122, 124. The ADCs 120, 122, 124 also include clocks that operate at a frequency of Fs/N, and include a phase of approximately (360/N)*(i−1). The delayed phase relationships of the clock signals result in digital samples from the ADCs which occur at a frequency of Fs. The result is an effective sampling frequency of Fs. N is the number of time interleaved ADCs and T is the period of the effective sampling frequency Fs.
The time interleaved architecture of FIG. 1 is fully sub-sampled (that is, sub-samples are generated by each of N sample and hold circuits, and processed by ADCs). Time interleaved architectures are useful for applications in which the desired sampling frequency Fs is higher than available individual ADCs or sample and hold circuits can operate. Each individual ADC and sample and hold circuit must only operate at a clock frequency of Fs/N.
The time interleaved ADC architecture of FIG. 1, however, has several limitations. For example, this time interleaved ADC architecture can suffer from gain errors, offset errors and phase timing errors, resulting in degradation of the signal to noise (SNR) of the combined sub-sample signals.
Generally, N interleaved ADCs require at least N operational amplifiers, in which each ADC includes at least one operational amplifier. Operational amplifiers dissipate a relatively large amount of power. Therefore, time interleaved ADC systems can dissipate more power than desired.
It is desirable to have a method and apparatus for high-speed analog to digital conversion of an analog signal. It is desirable that the method and apparatus dissipate lower amounts of power than existing ADC systems, and eliminate the disadvantages described above.